Senior ASIC Verification Engineer — SystemVerilog/UVM Expert

Empiric is seeking 5+ ASIC Verification Engineers for a global semiconductor manufacturing project. You will drive verification strategy, build advanced UVM/SystemVerilog testbenches, and own verification plans for SoC/IP blocks.

The role is based in Bristol or Cambridge with a 12-month rolling contract and a start in December. You should bring strong UVM/SystemVerilog expertise, experience with constrained-random stimulus, coverage-driven verification, and good collaboration with RTL teams to

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